The present invention relates to a flip chip semiconductor assembly for mounting a chip to a substrate via solder bumps. More particularly, it relates to a flip chip assembly in which a base layer is disposed between the chip and solder bumps to reduce the thermal expansion coefficient differential at the juncture of the chip and the substrate.
A flip chip assembly involves mounting at least one bare silicon chip to a circuit board or laminate substrate. FIG. 1, for example, shows a typical prior art flip chip assembly device 8. Referring to FIG. 1, each silicon chip 10 has at least one (and likely a plurality on bond pad electrodes 12 formed on its active surface. A plurality of solder bumps 14 are formed on the pads, the solder bumps typically projecting from the pad at a height of approximately 100 xcexcm. The chip 10 is mounted on the circuit substrate 16 by connecting the solder bumps 14 to the metallization pattern fabricated on the substrate, e.g., via substrate electrodes 18. The flip-chip technique is used in high performance devices and portable electronics to achieve devices that are low in weight, have high functionality, and are low in cost.
A drawback with the flip chip assembly, however, relates to differences in the thermal expansion coefficients of the chip 10 and the substrate 16. The temperature of a semiconductor chip typically will rise during operation. Heat generated from the chip will be transmitted to the substrate through the solder bumps, thus raising the temperature of the substrate. The chip and substrate will then thermally expand. Often with flip-chip semiconductor devices, there will be a difference between the thermal expansion coefficient of the chip and the substrate. The chip is generally comprised of silicon (with a thermal expansion coefficient of approximately 2.5-3.0 ppm/xc2x0 C.) and the substrate is often comprised of a fiber reinforced material, laminated glass plates impregnated with epoxy (with a thermal expansion coefficient of approximately 16-18 ppm/xc2x0 C.) or a ceramic substrate (with a thermal expansion coefficient of approximately 6 ppm/xc2x0 C.). Thermal stresses caused by this differential will concentrate in the solder bumps, causing premature failure of the solder bumps and degrading the long-term reliability of the semiconductor device.
To enhance the life of a flip-chip device, underfill epoxy materials have been used and placed between the chips and the substrate. However, the use of underfill materials requires extra processing, making the assembly process cumbersome and time-consuming. Underfill epoxy materials are also expensive.
As may be appreciated, those in the field of communications systems and in particular semiconductor devices continue to seek to develop new configurations that improve efficiency of manufacture and device performance. These and further advantages of this invention may appear more fully upon consideration of the detailed description below.
Summarily described, the invention embraces a semiconductor device comprising a semiconductor chip with its active side mounted on a substrate. The substrate has a predetermined thermal expansion coefficient different from that of the chip. To address the thermal expansion coefficient differential between the substrate and the chip, a monolithically-deposited base layer with two major surfaces is placed on the chip, the first major surface of the base layer being disposed on the active side of the chip and the second major surface of the base layer being disposed adjacent the substrate. At least one bond pad is disposed on the chip and coupled to the second major surface of the base layer. Solder bumps are disposed over the base layer and coupled to the bond pads. The solder bumps experience an effective thermal expansion coefficient which depends on the base layer thickness, and the base layer reduces the thermal expansion coefficient differential at the junction of the chip and the substrate. The base layer is preferably comprised of a polymeric material and may be deposited on a wafer level.
The invention further pertains to a method of preparing a plurality of semiconductor chips for mounting to circuit substrates. The method comprises providing a plurality chips on a wafer, each of which chip has at least one bond pad thereon. A polymer layer is monolithically deposited over the plurality of chips and bond pads, and then the polymer layer is removed in the regions of the bond pads to expose the bond pads. An interconnect metallic layer is placed over the plurality of chips to connect the bond pads to the surface of the polymer layer, and solder bumps are placed on the interconnect metallic layer.